Код:
ispLEVER Auto-Make Log File
--------------------------
Updating: Create Fuse Map
Start to record tcl script...
Finished recording TCL script.
Starting: 'C:\ispLEVER_Classic1_7\ispcpld\BIN\sch2blf.exe -sup "1ffd_lock_v2.sch" -err automake.err -gui'
Done: completed successfully.
Starting: 'C:\ispLEVER_Classic1_7\ispcpld\BIN\iblflink.exe "1ffd_lock_v2.bls" -o "1ffd_lock_v2.bl0" -ipo -family -err automake.err -gui'
BLIFLINK Top-Down Design Linker
ispLEVER Classic 1.7 Copyright(C), 1992-2005, Lattice Semiconductor Corporation. All rights reserved
Portions Copyright(c), 1992-1999, Vantis Corporation
Portions Copyright(C), 1993-1998, Data I/O Corporation
Portions Copyright(C), 1997-1998, MINC Washington Corporation
Portions Copyright(C), Alan Phillips, Lancaster University Computer Centre 1992-1998
Top-level file: '1ffd_lock_v2.bls'
Instantiating primitives...
Linking 'C:\ispLEVER_Classic1_7\ispcpld\lib5\g_2and.bl1'
Linking 'C:\ispLEVER_Classic1_7\ispcpld\lib5\g_2nor1.bl1'
Linking 'C:\ispLEVER_Classic1_7\ispcpld\lib5\g_2or.bl1'
Linking 'C:\ispLEVER_Classic1_7\ispcpld\lib5\g_4and.bl1'
Linking 'C:\ispLEVER_Classic1_7\ispcpld\lib5\g_4and2.bl1'
Linking 'C:\ispLEVER_Classic1_7\ispcpld\lib5\g_clkbuf.bl1'
Linking 'C:\ispLEVER_Classic1_7\ispcpld\lib5\g_d.bl1'
Linking 'C:\ispLEVER_Classic1_7\ispcpld\lib5\g_input.bl1'
Linking 'C:\ispLEVER_Classic1_7\ispcpld\lib5\g_output.bl1'
Hierarchical BLIF: '1ffd_lock_v2.bl0'
BLIFLINK complete. Time: 1 second
Done: completed successfully.
Starting: 'C:\ispLEVER_Classic1_7\ispcpld\BIN\iblifopt.exe -i "1ffd_lock_v2.bl0" -o "1ffd_lock_v2.bl1" -red bypin choose -sweep -collapse none -pterms 8 -family -err automake.err -gui'
BLIFOPT Open-ABEL Optimizer
ispLEVER Classic 1.7 Copyright(C), 1992-2005, Lattice Semiconductor Corporation. All rights reserved
Portions Copyright(c), 1992-1999, Vantis Corporation
Portions Copyright(C), 1993-1998, Data I/O Corporation
Portions Copyright(C), 1997-1998, MINC Washington Corporation
Portions Copyright(C), Alan Phillips, Lancaster University Computer Centre 1992-1998
U.C. Berkeley, SIS Ver. 1.0, supported by Lattice Semiconductor Corp.
Reading Open-ABEL 2 file 1ffd_lock_v2.bl0...
Performing 'bypin choose' optimization...
Writing Open-ABEL 2 (BLIF) file 1ffd_lock_v2.bl1...
BLIFOPT complete - 0 errors, 0 warnings. Time: 1 seconds
Done: completed successfully.
Starting: 'C:\ispLEVER_Classic1_7\ispcpld\BIN\iblflink.exe "1ffd_lock_v2.bl1" -o "1ffd_lock_v2.bl2" -omod 1ffd_lock_v2 -family -err automake.err -gui'
BLIFLINK Top-Down Design Linker
ispLEVER Classic 1.7 Copyright(C), 1992-2005, Lattice Semiconductor Corporation. All rights reserved
Portions Copyright(c), 1992-1999, Vantis Corporation
Portions Copyright(C), 1993-1998, Data I/O Corporation
Portions Copyright(C), 1997-1998, MINC Washington Corporation
Portions Copyright(C), Alan Phillips, Lancaster University Computer Centre 1992-1998
Top-level file: '1ffd_lock_v2.bl1'
Hierarchical BLIF: '1ffd_lock_v2.bl2'
BLIFLINK complete. Time: 1 second
Done: completed successfully.
Starting: 'C:\ispLEVER_Classic1_7\ispcpld\BIN\iblifopt.exe 1ffd_lock_v2.bl2 -red bypin choose -sweep -collapse all -pterms 8 -err automake.err -gui'
BLIFOPT Open-ABEL Optimizer
ispLEVER Classic 1.7 Copyright(C), 1992-2005, Lattice Semiconductor Corporation. All rights reserved
Portions Copyright(c), 1992-1999, Vantis Corporation
Portions Copyright(C), 1993-1998, Data I/O Corporation
Portions Copyright(C), 1997-1998, MINC Washington Corporation
Portions Copyright(C), Alan Phillips, Lancaster University Computer Centre 1992-1998
U.C. Berkeley, SIS Ver. 1.0, supported by Lattice Semiconductor Corp.
Reading Open-ABEL 2 file 1ffd_lock_v2.bl2...
Node N_50 has been collapsed.
Node N_42 has been collapsed.
Node N_43 has been collapsed.
Node N_44 has been collapsed.
Node N_45 has been collapsed.
Node N_46 has been collapsed.
Node N_48 has been collapsed.
Node N_39 has been collapsed.
Node N_35 has been collapsed.
Node N_36 has been collapsed.
Node N_8 has been collapsed.
Node N_9 has been collapsed.
Node N_11 has been collapsed.
Node N_12 has been collapsed.
Performing 'bypin choose' optimization...
Writing Open-ABEL 2 (BLIF) file 1ffd_lock_v2.bl3...
BLIFOPT complete - 0 errors, 0 warnings. Time: 2 seconds
Done: completed successfully.
Starting: 'C:\ispLEVER_Classic1_7\ispcpld\BIN\idiofft.exe 1ffd_lock_v2.bl3 -pla -o 1ffd_lock_v2.tt2 -dev p16v8 -define N -err automake.err -gui'
DIOFFT Flip-Flop Transformation program
ispLEVER Classic 1.7 Copyright(C), 1992-2005, Lattice Semiconductor Corporation. All rights reserved
Portions Copyright(c), 1992-1999, Vantis Corporation
Portions Copyright(C), 1993-1998, Data I/O Corporation
Portions Copyright(C), 1997-1998, MINC Washington Corporation
Portions Copyright(C), Alan Phillips, Lancaster University Computer Centre 1992-1998
Input file: 1ffd_lock_v2.bl3.
Output file: 1ffd_lock_v2.tt2.
Cross reference file: 1ffd_lock_v2.xrf.
.Note 13708:
Register 'TRIG_Q' polarity changed, powerup value inverted.
.Note 13708:
Register 'N_40' polarity changed, powerup value inverted.
....
Shortening signal names...
Writing signal name cross reference file 1ffd_lock_v2.xrf...
DIOFFT complete. - Time 0 seconds
Done: completed successfully.
Starting: 'C:\ispLEVER_Classic1_7\ispcpld\BIN\fit.exe 1ffd_lock_v2.tt2 -dev p16v8 -str -err automake.err -gui'
FIT Generic Device Fitter
ispLEVER Classic 1.7 Copyright(C), 1992-2005, Lattice Semiconductor Corporation. All rights reserved
Portions Copyright(c), 1992-1999, Vantis Corporation
Portions Copyright(C), 1993-1998, Data I/O Corporation
Portions Copyright(C), 1997-1998, MINC Washington Corporation
Portions Copyright(C), Alan Phillips, Lancaster University Computer Centre 1992-1998
Input file: '1ffd_lock_v2.tt2'
Note 4200: Nodes in '1ffd_lock_v2.tt2' file have been replaced with pins.
Device 'p16v8'
Note 4161: Using device architecture type P16V8R.
Note 4046: Signal N_40 (which has no OE) has been
assigned to pin 16 (which has pin OE).
Note 4046: Signal TRIG_Q (which has no OE) has been
assigned to pin 13 (which has pin OE).
Design FITS
Pin-assigned pla: '1ffd_lock_v2.tt3'
FIT complete. Time: 1 second.
Done: completed successfully.
Starting: 'C:\ispLEVER_Classic1_7\ispcpld\BIN\fuseasm.exe 1ffd_lock_v2.tt3 -dev p16v8 -o 1ffd_lock_v2.jed -ivec NoInput.tmv -rep 1ffd_lock_v2.rpt -doc brief -con ptblown -for brief -err automake.err -gui'
FUSEASM Fusemap Assembler
ispLEVER Classic 1.7 Copyright(C), 1992-2005, Lattice Semiconductor Corporation. All rights reserved
Portions Copyright(c), 1992-1999, Vantis Corporation
Portions Copyright(C), 1993-1998, Data I/O Corporation
Portions Copyright(C), 1997-1998, MINC Washington Corporation
Portions Copyright(C), Alan Phillips, Lancaster University Computer Centre 1992-1998
Note 5144: Could not open vector file NoInput.tmv
Input file: '1ffd_lock_v2.tt3'
Device: 'P16V8R'
Building model...
Choosing best polarities...
Mapping equations...
.
9 of 64 terms used; 0 vectors loaded
Programmer load file: '1ffd_lock_v2.jed'
Generating report...
Report file: '1ffd_lock_v2.rpt'
FUSEASM complete. Time: 1 second
Done: completed successfully.
Starting: 'C:\ispLEVER_Classic1_7\ispcpld\BIN\synsvf.exe -exe "C:\ispLEVER_Classic1_7\ispvmsystem/ispufw" -prj 1ffd_lock_v2 -if 1ffd_lock_v2.jed -j2s -log 1ffd_lock_v2.svl -gui'
Need not generate svf file according to the constraints, exit
Done: completed successfully.